1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a composite semiconductor substrate that includes a single crystal substrate of an insulating material and a single crystal layer of a compound semiconductor material that is provided thereon.
2. Description of the Related Art
Compound semiconductor devices are studied intensively in relation to super-fast semiconductor devices. By constructing semiconductor devices on a compound semiconductor layer, one can enjoy the excellent electronic properties pertinent to the compound semiconductor material, such as large electron mobility, formation of a two-dimensional electron gas at the heterojunction interface formed between different semiconductor layers, interaction with optical radiation by causing a direct transition of electrons and holes, and the like. Thus, various semiconductor devices such as HEMT or MESFET are fabricated on a GaAs substrate, a typical group III-V compound semiconductor material, or a mixed crystal thereof.
In order to maximize the operational speed of these semiconductor devices, efforts are made to reduce the size of the device, in addition to the effort in search of an optimum composition of the semiconductor material that is used for the semiconductor device. Currently, semiconductor patterns having a size of less than 0.5 .mu.m can be formed with reliability by using the electron beam exposure process.
On the other hand, such a miniaturization, when undertaken excessively, tends to invite various unwanted problems, such as a short channeling effect, soft error, side gate effect, and the like, wherein the short channeling effect occurs when carriers are urged away from the channel region of a semiconductor device toward the interior of a semiconductor layer on which the device is formed because of a large electric field that is established vertically to the surface of the semiconductor layer. It should be noted that such a large electric field is induced because of the excessively reduced size of the semiconductor device.
The soft error, on the other hand, occurs because of the incidence of high energy particles, such as .alpha. particles that cause an excitation of electrons and holes in the semiconductor layer on which the semiconductor device is formed. The carriers thus excited tend to diffuse into a device region at the surface of the semiconductor layer and affect the operation of the device. The problem of soft error is particularly serious in memories having large integration densities or devices that are used in a radioactive environment such as a satellite.
The side gate effect is a phenomenon that is pertinent to compound semiconductor devices, wherein the threshold level of a device such as a FET changes in response to a voltage that is applied to an adjacent device. In this case, it is believed that electron-hole pairs are created due the large electric field associated with the channel region of the device, and recapturing of the excited electrons and holes in the vicinity of the channel region is responsible for the undesirable variation of the threshold level.
In order to avoid the aforementioned various problems, use of the so-called SOI (semiconductor-on-insulator) structure has been studied. In the silicon devices, it has been practiced to bond a silicon single crystal substrate on a silicon oxide layer to form the desired SOI structure.
FIGS. 1(A)-1(D) show the conventional process employed in the silicon devices for forming the SOI structure.
Referring to the drawings, two silicon substrates 1 and 2 are oxidized separately in a step of FIG. 1(A) to form silicon oxide films 3 and 4 respectively on the silicon substrates 1 and 2. Next, the two silicon substrates 1 and 2 thus covered with the silicon oxide films 3 and 4 are contacted with each other intimately and placed on a heating fixture 7 that may be formed of SiC. See FIG. 1(B). There, while energizing the heating fixture 7, a voltage impulse 5 is applied across the two substrates 1 and 2, and the electric field induced in association with the voltage impulse 5 exerts a force between the two contacting substrates such that the substrates 1 and 2 establish a firm mechanical contact. Thereby, the dangling bonds at the surface of the silicon oxide films 3 and 4 establish a stable bond with each other and a structure shown in FIG. 1(C) is obtained. After annealing in an inert atmosphere, the interface between the silicon oxide films 3 and 4 substantially disappears. Next, one of the silicon substrates, for example the substrate 1, is subjected to a mechanical lapping and polishing process to expose the silicon surface, and the polishing process is continued until the thickness of the substrate 1 reaches a predetermined or desired level.
In the case of compound semiconductor devices, however, the foregoing procedure for a silicon substrate is not applicable. It should be noted that formation of a stable oxide film to cover the compound semiconductor substrate such as GaAs is generally not possible.
So far, various studies have been made to achieve an SOI structure for compound semiconductor substrates. For example, Lehmann et al. (Lehmann, V., Mitani, K., Stengel, R., Mii, T., Goesele, U., Jpn. J. Appl. Phys. vol. 28, 1989, L2141-L2143) describes an attempt for bonding InP and GaAs substrates on a silicon substrate. As reported therein, it has been observed that the substrate experiences cracking or separation when the temperature for bonding has risen above 160.degree. C. Obviously, this unsatisfactory result arises due to the mismatching in the thermal expansion coefficient between both substrates. The bonding was possible only in the temperature range below 140.degree. C., while it is obvious that such a low temperature is insufficient for causing bonding in the atomic scale.
Another approach to achieve an SOI structure in the compound semiconductor material would be to grow a compound semiconductor layer on a single crystal substrate of an insulating material. In fact, there have been an extensive study for growing a GaAs layer epitaxially on an insulating single crystal substrate such as sapphire. See Kasai et al., for example (Kasai, K., Kasai, K., Ozeki, M., J. Appl. Phys. vol. 60, 1986, pp. 1-5). Sapphire is selected because it has a thermal expansion coefficient that is close to the thermal expansion coefficient of GaAs in the temperature range above 300.degree. C. See FIG. 2 showing the temperature dependence of the thermal expansion coefficient for various materials.
However, such a growth of the compound semiconductor layer has turned out to be unsuccessful for the fabrication of compound semiconductor devices. More specifically, it turned out that the epitaxial growth of the GaAs layer is possible only on the C-surface of the sapphire crystal shown in FIG. 3, while generally a available large diameter substrate of sapphire shows the R-surface as the principal surface. Further, the GaAs epitaxial layer thus grown on the C-surface inevitably shows the (111) oriented principal surface. As the (111) surface of GaAs does not provide an adequate, defect-free surface contrary to the usual (100) surface that is used extensively for constructing high speed devices such HEMTs, and in view of the fact that there still exists a lattice mismatch as large as 19%, the possibility of constructing high performance semiconductor devices on the GaAs layer grown epitaxially on a sapphire substrate is no longer studied intensively among persons skilled in the art.
Further, the inventor of the present invention has conducted research to bond a GaAs substrate on a silicon substrate that carries a silicon oxide film thereon. In the experiment, it was confirmed that the bonding between the substrates occurs successfully at a temperature of 700.degree. C., while it was also confirmed that the substrate starts to crack when the temperature has been reduced below about 300.degree. C. The foregoing observation confirms the recognition in the art of GaAs-on-Si, that an extensive formation regarding dislocation occurs when the GaAs epitaxial layer grown on a silicon substrate is cooled below a temperature of about 300.degree. C.
From the foregoing experimental evidence, one has to become pessimistic about the possibility of forming an SOI structure by growing a GaAs single crystal layer on a silicon substrate that carries thereon a silicon oxide film.